Computer Architecture: Fundamentals of Quantitative Design and Analysis

Today, less than $500 will purchase a compute that has more performance, main memory and storage than a 1985 computer over 1 million dollars. This has come from both advances in technology and innovation in computer design. Performance improvement has grown around 25% a year, and the introduction of the microprocessor led to 35% performance improvement growth a year. This led to many more microprocessors, and eliminated the need for an assembly-level programming language for compatibility. Creation of Linux and vendor-independent operating systems has lowered the cost in bringing a new architecture, since everything is now abstracted much better.

RISC, or reduced instruction set computer, was made possible, which exploited both instruction-level parallelism and the use of caches, through pipelining, and organizations/optimizations, respectively. The cost performance improvement led to new classes computers such as smart phones, personal computers, and workstations. The improvement of semiconductors has also led to the dominance of microprocessor computers, which make up supercomputers. The improvement since 1978 allowed programmers to trade performance for productivity, and there are compilers to bridge the gap between performance and productivity. The software as a service (SaaS) is also used over the internet. Speech, sound, images, and video have been incorporated, and an example is the Google Goggles.

Computer architecture goes from instruction-level parallelism to thread-level parallelism and request-level parallelism prevalent in parallel scale computers. Data, threads, and requests can be run in a parallel manner. Computer architecture uses programs, experimentation, and simulation as its tools.

The mobile device is designed to have low cost, good media performance, and responsiveness. A desktop is designed to have good graphics, low price-performance ratio, and efficient energy. Servers are designed for throughputs, availability, scalability, and energy. A Cluster is designed for good performance-to-price ratio, high throughput, and good energy proportionality. Embedded systems are designed to be low-cost with application-specific performances. Servers must be able to grow in response to increasing amount of data, and the bandwidth must also increase for efficient throughput in terms of transactions per minute. Clusters are collections of servers connected by local area networks (LANs) to act as a single larger computer, with each node running as its own operating system, and the nodes communicating through a network protocol. 80% of the cost of a warehouse is powering and cooling the computers inside. As a result, it's effective to look at how much you can save due to the efficiency of the system, since certain gears need to be placed every year. Warehouse scale computer have a higher potential loss, so the availability is critical and relies on a software layer and cache and uses cheap stuff. Supercomputers emphasize floating-point performance, which leads to much faster internal networks. Embedded computers contain 8 and 16 bit processors that are cheap and 32 bit, and even 64 bit processors. 

Parallelism is the driving force of computer design across all four classes computers. 

There is data-level parallelism (many data items can be operated simultaneously) and task-level parallelism (tasks of work are created that can operate independently and largely in parallel. Instruction-level parallelism exploits the data-level at models levels by using pipelining. Vector architectures apply a single instruction to collections of data in parallel. Thread-Level Parallelism exploits data-level or task-level parallelism that allows for interaction among threads. Request-level parallelism exploits it in tasks specified by the programmer or the operating system. A single instruction stream/single data stream is the uniprocessor. Single instruction stream multiple data streams is where the same instruction is executed by multiple processor, and apply operations to multiple items of data in parallel. There is a control processor, with children processors, with its data memory, since we are dealing with data parallelism here, used often in GPUs. There are no processor for a single data stream and multiple instruction streams. Multiple instruction and data streams is more flexible than single instruction multiple data strings, but is more expensive. They have higher levels of overhead and use thread and request level parallelism. There are many processors with all the classes (SISD, SIMD, MIMD).

A computer architect needs to determine what attributes are important for a new computer and the design a computer to maximize these aspects. The architect or designer's job is based on instruction set design. There is ARM, which is used in embedded systems, 8086 and MIPs. All desktop and server computers use byte addressing to access memory operands, and some objects might be aligned. Operands are usually either register or memory locations with 16 registers/general purpose and 32 GP/FP for 80x86 and the MIPs, respectively. Addressing modes are register, intermediate and displacement in order to form memory addresses. ARM has 3 MIPs addressing plus the PC relative addressing as well as the sum of 2 registers, and autoincrement and autodecrement. These instruction set support up to 64 bits and 80 bits for 80x86. There are data transfer, arithmetic, and control operations as well as floating point and MIPS is a relatively simple easy-to-understand pipeline architecture. ISAs also have a lot of control flow instructions, conditional branches, unconditional jumps, procedure calls and returns which all use PC-relative addressing. ARM has return address on register, while 80x86 has the return address on the memory. There is also a fixed length and variable length encoding which is usually 32 bits long, while 80x86 can be anywhere from 0 to 18 bytes. MIPS64 is the dominant ISA, and ARM is a popular example of this. 

I'm not going to type everything, so here's the MIPs sheet for reference.

Computer has 2 parts of implementation, which is the organization and hardware. Organization is the high-level aspects of a system and microarchitecture is the same as organization. Computers can have the same ISAs but different organizations. 

Hardware is the specifics of the computer, the logic, and the packaging technology of the computer, with clock rates and stuff like that. Architecture covers ISA, organization, and hardware. Architects must determine the functional requirements of a computer. We also need to see the potential future cost and cost-benefit analysis of the architecture. We need to see if a software is compatible on programming language and if the computer is compatible with binary code. We also need to know the size of the address space and how our device will perform both memory management and protection. Finally, an architecture needs to support, floating points, interfaces, operating systems, networks, and programming languages. 

Historically, transistor density increased around 35% a year quadrupling somewhat over 4 years, and the increase in the size are less predictable over time. Moore's law has the number of chips growing around 40-55% a year. Semiconductor DRAM is the foundation of main memory, with growth that is dramatically slowed down. The standard semiconductor device is the storage device in PMDs, and the capacity of flash is doubling every 2 years.  The disk improvement only sees to 5% capacity increase per year, because it is harder to add more platters. Disks are much more cheaper than other various parts of RAM. Network performance depends on performance of switches and transmission system. 

Bandwidth or throughput is the total number of work done at a given time. Performance has seen the greatest gains in both bandwidth and latency. Then capacity, but bandwidth has outpaced latency, which is the delay before the transfer of data begins following an instruction. Many computers are slowing heading for a single chip for all processors. The feature size is the minimum size of the transistor or wire that a chip is located in. The density of transistors increases quadratically with the linear decrease in feature size. Device sizes shrink quadratically as feature sizes shrink. Density improvements have supported the introduction of multiple processors per chip and wider SIMD units and innovations. The signal delay of a wire in creases in the proportion to the product of its capacitance and resistance. Wires get shorter as feature sizes shrink, but resistor and capacitor length get worse. However, wire delay has been a major design obstacle for larger integrated circuits. Power plays an even greater role than wire delay now, and wire delay just consumes more clock cycles.