GPIO Pins
These GPIO pins are used to interact with external devices, such as LEDs and push buttons.
IO ports can be configured to either act as an input or an output. The voltage levels on the pins are converted to the corresponding value. 3.3V = 1, 0.0V = 0. For example, this is 0111. Note that the last switch is closed, connecting to ground.
In output, software writes logic to the port, which places voltages as a pin, and can be used to turn certain LEDs on. For example, placing more voltage on the left hand side will result in the LEDs not turning on because of the voltage differential and vice versa.
Pull up or pull down resistances set the state in the absence of a signal, an example of this is a push button. HiZ means software is unknown, and this is the state when IO pin is an input without any microprocessors driving it.
We can solve this by adding a pull up resistor, indicated by the first picture in this website.
Sometimes, you have to debounce a push button. To prevent this from happening:
We can debounce the button by adding a capacitor, since the voltage cannot change now due to the capacitor. Another method is to use software to debounce this button.
We can assume an application stops bouncing or is "debounced" after 2 readings of 0.
Analog Input Pins
Use these if you want to examine the voltage present in a pin as an Analog signal, such as a sine wave or EKG. We use this to examine the continuous nature of a signal, and this is done by quantization. Use an analog to digital converter to perform this operation. For example, the resolution for the analog to digital converted with 3 bits is 3.3/8 = 0.4125. There are 2^N distinct value if the number of bits of precision are N.
An application reconstruct a digital signal, and a sine wave will be digitized accordingly.
An ideal solution will sample the solution at an infinitely fast rate, but we should sample at over twice the highest frequency that is to be measured, called the Nyquist sampling rate.
Device Electrical Characteristics
Designers must evaluate if 2 components are electrically compatible with each other, which happpens if both devices can provide appropriate levels of logic 0 or logic 1. 1 is from 1.65 to 3.3 and 0 is below this. Read the datasheet to determine this.
VIH is the voltage level that is required for logic 1 and VIHMIN is the minimum that can represent logic 1. Max column indicates the maximum voltage to be supplied without causing data leakage. VIL is logic - and VILMAX is the maximum value for logic 0. Same for VOHMIN and VOLMAX, for outputs, where we determine the voltage the board will place on its pins.
We then need to determine when devices are compatible with each other. These devices are compatible if the minimum voltage that defines logic 1 is greater the maximum voltage that determines logic 0. This is called a gap margin. We predict how large the voltage spike that the system can tolerate.
Noise margin = min(VOHMIN - VIHMIN, VILMAX - VOLMAX). The system can malfunction if any of these traits are violated.
Current going into a device is positive, and vice/versa. Logic 1 sources a current in the output, while logic 0 sinks the pin with the output, which decreases VOHMIN and increases VOLMAX, respectively.
Interrupts
Some events don't follow a practical sequence of operation, are asynchronous, and happen at super random intervals. These are called interrupts, which alerts the microprocessor to top the previous event and accommodate to this events.
A uses see if a button is pushed, and it represents 2 passes throughout the loop. Interrupts allow how we examine a button. here is an example sequence with the green operation being the button examination. Next is interrupt service routine.
To make these routines short and fast, we queue the data and defer the bulk of the computationally expensive stuff to the main application. The new data is then placed into SRAM. The main method sets a global variable to false and begins to process the data placed in the ISR's queue.
An interrupt sets up a bit in the interrupt status register. The Microprocessor goes into handler mode and saves all the registers and program counter, called a context save. Then the microprocessor does a context restore and exits handler mode.
Polled interrupts sets an ISR and then goes to the master ISR, and then make a function call through the master ISR. Vector interrupts see the interrupt and loads an address specified in the vector table based on the device that caused the interrupt. However multiple interrupts can be active simultaneously. TO solve this microprocessors set priority levels which probably uses a heap or priority queue. The character volatile releases a computer to reread things. We then have to activate peripherals to achieve desired inputs.
A nested vector interrupt controller (NVIC) indicates we want to enable an interrupt from a given peripheral.
We enable the desired peripheral in the vector table. The application code will interrupt every x milliseconds (ex. Systick_config(frequency)).
We write the bit locations (the correct ones) to the corresponding interrupt control registers. To enable interrupts, write to the nested vector interrupt controller (NVIC).
Timers
These are devices used to set the interval between events. They determine how long a task is active before swapping to a new task. They can also perform PWM with LEDs to save power. They both have a register that contain the value of time and a reload register. The reload register determine the frequencies and decrements until the current register equals to zero. The reload register determines the number of clock cycles that have to go before the timer is called again.
Count down timer go until the reload register = 0 and the count up goes to the current register until the RELOAD register value is added.
A timer is periodic continues to count up and down and reload until the timer is turned off.
Prescalar sets the number of clock cycles before the count register decrements.
Real timers determine the date that some events occur, allowing us to schedule events to happen at specific dates.
Watchdog timers ensure that an embedded system is functioning properly. When it reloads, the microprocessor will reboot or suspend activity indefinitely. This is a fail safe method that resets the microprocessor when the normal flow of an application goes awry. We must figure out what to do when this timer expires.
UART
Serial Interfaces are shift registers that shifts data in or out one bit or time. starting with the least significant bit, resulting in their respective waveform.
We want serial interfaces to only contain a few pins, not N pins for N bits. We want additional clock cycles instead.
The UART consists of an RS and TX pin of 2 specific devices.
Rx and Tx pins are normally connected to shift registers, allowing UARD to transmit and receive data at the same time. The next byte of data is loaded into a transmit shift register when a transmit register is empty. The status register has a status bit when a new byte of data has been received. UART can also have other registers to configure its behavior.
'A' stands for asynchronous, since there is no common clock shared between the devices, but the devices need to agree on the data that is being sent and the speed of the data that is sent.
Both UARTs must receive data at the same rate, and this is configured in baud. Data also contains parity bit at times, to see if there is an error. For example an odd parity says an odd amount of bits need to be sent.
Rx and Tx are driven high when no data is being sent. bringing Tx low will indicate that data is about to be sent. Afterwards, data is shifted out until all the data has been transmitted. Then the parity bit, followed by the stop bit.
8N1 is 8 data bits, no parity bits, 1 stop bit.
However, there can be a problem, and there is inefficient polling. There are some techniques to reduce the polling time.
Interrupts can be generated to have the main application perform other tasks when the UART is inactive. There is a receive interrupt when the new data has arrived. ISR places data in SRAM, alerts main application and clears the interrupt.
Some UART buffers generate interrupt when the transfer buffer is empty. We avoid the situation where application is not transmitting data. To do this the UART handler disables its transmit interrupt when the circular buffer is empty and adds the data to queue when wishing to send data and reenables the interrupt, so there is always data being processed.
FIFOs are a fixed size, so there is a wait if the FIFO can't hold a byte string. Circular Buffers stay in SRAM to buffer the characters destined for UART, having 80% of memory to store characters in the linked list. The rate added cannot be much greater than the rate removed.
When the receive timeout interrupt is active the ISR removes entries until FIFO is empty then clear the interrupts and return.
The application also grabs the data from the circular buffer and adds it to FIFO, and there is a form control here.
When the transmit data is empty the UART removes data from the transmit circular buffer. The transmit empty interrupt is disabled when the application has no data to send. If circular buffer is empty and FIFO not full, reenable transmit interrupts and place data into FIFO. If there is data in a circular buffer, ISR consumes characters until FIFO is full or buffer is empty.
If we cannot make sure these operations can be completely separate then we have a race condition where main buffer tries to modify the elements of a circular buffer. To solve this, have the main function temporarily disable interrupts.
I2C
The I2C bus can support multiple master and slave devices on the same bus. This reduces the number of pins on the microprocessor.
The I2C bus has the data (SDA) and clock (SDA) lines. When transistor is unconnected to a pin, the pullup resistor pull line up to VCC (logic 1.)
This open drain pin is a good choice for bidirectional data buses, where the pullup resistor limits the current when one device places a logic 1 and another device drives a logic 0. There can be multiple slaves and multiple masters in an I2C bus.
I2CSDA and I2CSCL is on microcontroller. SDA is a bidirectional serial data line and SCL a bidirectional clock line, and the bus is considered idle when both lines are high. Check the data sheet for this.
Data is transmitted through the most significant bit first, and can be written and read from an external device by specifying internal registers of the peripheral device. Each byte of data needs to be acknowledged for the data transaction to complete, present when many devices are present in the I2C bus.
Each byte needs to be acknowledged through ACK in order for the data transaction to complete. SDA and SCL lines are pulled high when there is no activity. The SDA will have to be low while SCL is high to signify the beginning of a data transaction.
All these transactions have an acknowledge cycle that is generated by a master, which the transmitter releases the SDA line and receiver must pull SDA down during this clock cycle.
When the receiver does not acknowledge the slave address, SDA must be high to abort the current transfer.
The master is responsible for acknowledging each transfer made by the slave, and signals the end of the data. An ack is generated at the end of an address once something is sent.
Stop is when SCL is high and SDA makes a low to high transition.
Each device is assigned an address in an I2C bus and the first byte transmitted is the address of the slave device being accessed, which consists of the device UD in data sheets. Pullup/pulldown resistors set a unique address to the device.
When multiple deices are placed on a bus, the hardware ensures the 2 devices don't have conflicting addresses. An 8 bit address represents a read/write bit, a 7 bit address does not.
SPI
SPI is a serial peripheral interface and is synchronous. It helps with increased data speed and is used by modern PCs to load the BIOs. There is increased data throughput, but also a requirement for more pins.
There is a higher transfer rate, because these 2 interconnected devices share a common clock. There is no over-sampling on a SPI bus at all. It also uses a master-slave configuration.
2 devices are interconnected by a simple SPI bus, and requires one of the devices have a clock to determine if the data is shifted. The master device generates the clock and determines when the data transactions occur. The master periodically polls the sensor. This consumes clock cycles, or a sensor can generate an interrupt on all the pins of the microprocessor. The sensor asserts the interrupt indicating it requires attention when the sensor tries to report data. The microprocessor generates an interrupt when the sensor asserts a specific pin.
There are 4 dedicated pins in the SPI. The clock is the rate at which data transfer occurs. The device with the slowest clock rate determines the maximum speed. MOSI is the master out/slave in to transfer data from slave device. MISO is master in slave out which receives data from the slave device. Both of these transfer first from the most significant bit.
There is also a /CS or active low chip select to frame the number of bytes being transmitted. There are no start or stop bits to determine when the data is valid, which allows faster transfer. Master controls the /CS line, but /CS can also be GPIO pin and software will determine the line's value.
Since the chip select ~CS1 is low for 32 clock cycles, it tells SPI that the transaction is 4 bytes lone. there are 4 bytes of data on MOSI transmitted and receive 4 bytes of data on the MISO.
SPI also must be configured to agree with how the clock behaves during periods of misbehavior.
Clock polarity determines if the clock is logic 0 or 1 when the data isn't being sent. Clock is logic 0 when polarity is 0 and logic 1 when the clock has polarity 1, when inactive. If phase = 0, the most significant bit is transferred first, on first edge, and if phase = 1 it is transmitted in the second edge of the clock. There are 4 different SPI methods as a result, and the microprocessor will need to be configured by the SPI mode supported by the slave device.
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